The NI Hardware Test Sequencer IP provides a framework for performing real-time test execution on a LabVIEW FPGA user-programmable FPGA with minimal host interaction.

The IP executes a list of instructions, which are provided from the host. Each instruction contains a condition and an action, and corresponding data for each. Once a condition has been met, the corresponding action is executed. Once both the condition and action have been completed, the sequencer moves to the next instruction.