Some applications require offloading the data from the FPGA in the VST to another device. This can be accomplished in several ways: DMA FIFOs to a host system, Peer-to-Peer DMA FIFOs to other devices in a PXIe system, or through the front-panel DIO of the VST. Or, some applications require transferring data to another clock domain for processing, which can be done using local FIFOs. This IP provides an API to control the reading and writing of the FIFOs used in these applications.