This VI must be placed in a single-cycle timed loop for guaranteed behavior.

Serial Peripheral Interface (SPI) buses are commonly used to communicate between a controller (master) device and a target (slave) device. In general, SPI buses require four lines for communication: chip select/clock enable, serial clock, master serial data out (MOSI), and master serial data in (MISO). In some cases only a subset of these lines are used; some devices multiplex both MOSI and MISO onto a single bidirectional data line. This IP includes LabVIEW FPGA code for both an SPI master and an SPI slave.