This IP contains a memory to hold sets of U32 data values, or instructions. Instructions are grouped into sequences, and there may be one or more sequences in the memory. Events on the FPGA cause an entire sequence of instructions to be sent to the downstream IP, accommodating back-pressure or flow control. After a sequence is generated, the IP advances to the next sequence in the memory. Once all sequences have been generated, the IP returns to the first sequence, enabling looping.