SPI is a commonly used communication protocol for both integrated circuit communication and embedded sensors. The protocol operates in full duplex with a single master and multiple slaves per port. This allows the flexibility of communicating with several different devices through a single port where each device can have its own clock rate and command set.

The SPI bus in this document is implemented using LabVIEW FPGA to perform the bus mastering and clocking signals. A single-cycle timed loop (SCTL) is used to perform each step of communication between the SPI master (LabVIEW FPGA VI) and up to 8 slave devices per port. Multiple ports can be created using the same FPGA VI and interface to a host program.

The bus is encapsulated in a higher level LabVIEW FPGA VI, which utilizes a state machine to perform intermediate communication between each SPI port and a host interface. This VI synchronizes the host interface and SPI ports and multiplexes data sent from the host to a specified port.